The present invention relates to a method for manufacturing a semiconductor power device. With the method, the ON resistance of the device is improved.
A variety of methods have been proposed to reduce the ON resistance of a power device. In the methods, the resistance of the semiconductor layer included in the device is decreased. For example, JP-B-2513055, corresponding U.S. Pat. No. 5,242,862, of which is discloses a method for manufacturing a vertical semiconductor power device. The method includes the following steps. At first, a device layer, which includes MOSFETs, and a front surface electrode are formed on the front surface of a semiconductor wafer. Then, the wafer is evenly ground from back surface, which is opposite to the front surface, such that the wafer has a thickness of 200 to 450 μm. Next, a back surface electrode is formed on the back surface of the wafer. The semiconductor layer included in the power device is thinned by the grinding, so the resistance of the semiconductor layer is decreased. As a result, the ON resistance of the power device is reduced.
However, with the method according to the publication, the fragility of the wafer increases drastically if the wafer is ground to thinner than 200 μm. As a result, the yield of the power device is lowered due to the wafer breakage during the grinding or when an adhesive film that is stuck to the wafer is peeled from the wafer. Therefore, it is substantially impossible to make the wafer thinner than 200 μm by the method according to the publication. That is, it is substantially impossible to drastically reduce the ON resistance of the power device by the method according to the publication.
On the other hand, JP-A-5-121384 discloses a method, with which the above problem can be solved. In the method, a semiconductor wafer is thinned only at its central area from the back surface using a polishing machine, which includes a grindstone having a diameter smaller than that of the wafer, and a rim is formed at the periphery of the wafer after polishing. The wafer is not thinned in the periphery, so the rim has the original thickness of the wafer to reinforce the wafer. Therefore, it is possible to make the wafer thinner than 200 μm.
However, with the method disclosed in JP-A-5-121384, the wafer is damaged at its polished back surface. Accordingly, the contact resistance between the back surface and a back surface electrode, which is formed on the back surface, is relatively high. In addition, it is substantially impossible to form a beam in the central area for reinforcing the central area because the wafer is polished with the grindstone, which has a diameter smaller than that of the wafer. As a result, if a wafer having a relatively large diameter needs to be polished, the wafer may break or warp. Therefore, in that case, the method disclosed in JP-A-5-121384 is less effective.